1. Field of the Invention
The present invention relates generally to the operation of a command queues and, more particularly, to the use of a stall mechanism in a command queue.
2. Description of the Related Art
In conventional computer architectures, there are a variety of devices that employ command queues, such as Direct Memory Access (DMA) devices. The command queues operate by receiving and storing commands issues by a processor or processing device. The commands are communicated through a pipeline to a command queue, where each command is entered into a command entry location or slot. Then, unroll logic issues each command out of the command queue. The problem is that the command queues are finite in depth.
Typically, command queues are inadequate to handle the number of commands in the pipeline. Hence, the command queues can have difficulty in handling back-to-back commands greater than the number of entry locations or slots available in the core of the command queue. The result is that a flush mechanism is typically employed. The flush mechanism causes an instruction unit to back up the code stream of commands when attempted command issuance fails. An instruction backs up the commands and attempts to retry the commands. The problem is that the command starts again at the fetch stage at the beginning of the queue. Restarting commands at the fetch stage can cause greatly increased latencies.
Therefore, there is a need for improving the operation of a flush mechanism in a command queue that addresses at least some of the problems associated with conventional methods and apparatuses for operating command queues.